Certain semiconductor devices include twin wells. A twin well includes a P well and an adjacent N-well. FIG. 1 depicts a conventional method 10 for providing a conventional twin well semiconductor device. The portion of the conventional twin well semiconductor device in which the P-well is to be formed is masked, via step 12. Step 12 includes forming a pad oxide over the surface of the wafer for the conventional twin well semiconductor device. Step 12 also includes depositing a nitride layer on the pad oxide over the surface of the wafer and providing a photoresist mask covering regions which are not to be implanted during formation of an N-well. Step 12 further includes removing the exposed portion of the nitride layer in regions in which the N-well is to be implanted. Consequently, the pad oxide is exposed in the regions in which the N-well is to be implanted, while the remaining nitride covers regions in which the P-well is to be formed. The photoresist mask may also be removed in step 12. The N-well is implanted, via step 14. Step 14 thus includes implanting with phosphorus, arsenic or another N-type dopant. The silicon nitride layer is sufficiently thick to prevent the N-type dopant from passing through the nitride in regions in which the P-well is to be formed. In addition, a photoresist mask, which is virtually congruent to the remaining nitride underneath, may optionally be retained as present in step 12 and used as mask in conjunction with the remaining nitride. Consequently, step 14 allows the N-well to be provided.
After implantation of the N-well, a LOCOS oxide is grown typically using a high temperature oxidizing ambient, via step 16. Prior to growing the LOCOS oxide, remaining photoresist is removed. The remaining nitride precludes the LOCOS oxide from being grown underneath, in regions in which the P-well is to be formed. The remaining nitride is then removed typically using a hot phosphoric etch bath, via step 18. A P-well is implanted typically using boron or another P-type dopant, via step 20. Because of the presence of the LOCOS oxide, the P-type dopant does not penetrate the N-well. The LOCOS oxide is then removed and the P-type implant activated, via step 22.
FIG. 2 depicts a conventional twin well semiconductor device 50. For clarity, the conventional semiconductor device 50 is not drawn to scale. The semiconductor device 50 is fabricated using the conventional method 10. The conventional semiconductor device 50 includes an N-well 52 and a P-well 56. Because the conventional method 10 is used, the N-well 52 and the P-well 56 are adjacent.
Although the method 10 can provide the conventional semiconductor device 50, one of ordinary skill in the art will readily recognize that the conventional semiconductor device 50 has serious drawbacks. In particular, the surfaces of the N-well 52 and P-well 56 are not coplanar. A step 60 exists between the surfaces of the N-well 52 and P-well 56. The step 60 adversely affects subsequent processing. For example, the step 60 may elevate electric fields and are associated with failures and defects, such as dielectric failure of a gate oxide that passes over a step. The step 60 may also cause out-of-focus conditions, which degrades imaging and reduces control over the properties of the conventional semiconductor device 50. The step 60 may also reduce the current carrying capacity of conductors which pass over the step 60 and reduce the mobility of charge carriers (electrons and/or holes) passing in the vicinity of the step 60. In addition, the step 60 may reduce the process window for subsequent chemical mechanical polishing (CMP). Moreover, the presence of the step 60 can result in the formation of stringers or unwanted pockets of material adjacent to them.
Accordingly, what is needed is a method and system for providing an improved twin well device. The present invention addresses such a need.